1. Field of the Invention
The present invention relates to test architectures and, in particular to cyclical cache chains, selective bypass scan chain segments, and blocking circuitry that can facilitate maintaining test application time over generations of technology.
2. Related Art
Scan compression refers to techniques of reducing the amount of data needed to test integrated circuits. Reducing the amount of data can advantageously reduce test application time on expensive ATE (automated test equipment). Reducing the amount of data can also advantageously reduce tester memory and allow for increased pattern counts, thereby extending the life of existing ATE equipment. Logic BIST (built-in self-test), which is known by those skilled in the art of test, can also facilitate significant data compression.
Scan compression can also achieve test application time reductions by reducing scan chain lengths. For example, FIG. 1 illustrates a test architecture 100 that includes a plurality of scan cells 103. Specifically, two scan inputs 101A and 101B can be provided to two scan chains, each scan chain having 12 serially-connected scan cells. The test architecture of FIG. 1 provides two scan outputs 102A and 102B.
FIG. 2 illustrates another test architecture 200 that includes the same number of scan cells 203 as test architecture 100, but increases the number of scan chains from 2 to 6. This increase in the number of scan chains can advantageously reduce the length of each scan chain to 4, thereby reducing the test application time by one-third (i.e. test application time=patterns×scan chain length). Notably, test architecture 200 can use the same scan interface as test architecture 100. That is, test architecture 200 provides two scan inputs 201A and 201B as well as two scan outputs 202A and 202B (which are generated by a compressor 205). An ATE generally has a limit on the scan chain length that can be analyzed. Because an ATE is extremely expensive and therefore is used for multiple technology nodes, the number of scan chains used for test has increased rather than increasing the scan chain length.
Note that in test architecture 200, a decompressor 204 can map scan inputs 201A and 201B (and/or their derivatives via logic and/or sequential elements, not shown for convenience) to the six scan chains. Thus, the values provided to scan cells 203 can have dependencies. For example, because scan inputs 201A and 201B can supply values to six scan cells per clock cycle, on average three scan cells would have the same (or inverted) values. Notably, increasing the ratio of the number of scan chains to the number of scan inputs would increase the dependencies. Such increased dependencies could increase the pattern count.
Thus, both scan chain length and pattern count can impact test application time. As a result, test application time can be reduced by minimizing pattern inflation, providing more scan chains, and/or partial shifting. Note that in partial shifting, a subset of the total number of scan chains directly receives top level scan inputs (i.e. from external sources, such as a pin) and the rest of the scan chains receive scan inputs from a decompressor.
Assuming ATPG (automatic test pattern generation) has maximum efficiency, pattern count can only be reduced by increasing the test data bandwidth to the decompressor such that ATPG can compact multiple patterns into one pattern. As noted above, creating more scan chains can increase the dependencies between values across scan cells, which may increase pattern inflation and perhaps diminish returns in the overall test application time. Increasing bandwidth to the decompressor can allow for more aggressive scan chain ratios if pattern inflation is limited. Partial shifting methods may result in the effective scan chain lengths varying on a per pattern basis, which does not work well with existing tester architectures.
Therefore, a need arises for increasing the test data bandwidth to the decompressor while minimizing scan cell dependencies, limiting pattern inflation, and ensuring compatibility with existing tester architectures.